[News] FOPLP Heats Up: ASE, Powertech Expand; TSMC Reportedly Preps 2026 CoPoS Pilot Line

According to Economic Daily News, fan-out panel-level packaging (FOPLP) is regarded as the next mainstream technology in advanced packaging. Key industry players—including foundry giant TSMC, semiconductor packaging and testing leader ASE, and memory packaging powerhouse Powertech—are actively investing in this area to tap into the growing demand for high-performance computing (HPC) chip packaging from major clients such as NVIDIA and AMD.

Industry sources cited in the report note that, compared to wafer-level approaches, panel-level fan-out packaging provides a larger substrate area and enables heterogeneous integration, helping to further miniaturize consumer electronic devices.

TSMC

The report states that TSMC’s fan-out panel-level packaging (FOPLP) technology is reportedly named CoPoS (Chip-on-Panel-on-Substrate), with production capacity planned for Chiayi. A pilot line is expected to be established in 2026, according to the report.

As the report notes, TSMC’s CoPoS technology is primarily aimed at AI and high-performance computing (HPC) applications. Sources indicate that mass production is expected by 2028. The process transforms CoWoS packaging into a panelized, square-shaped design, which is expected to significantly boost chip output, as the report indicates.

Notably, MoneyDJ highlights NVIDIA as the likely first big customer for TSMC’s CoPoS, while Economic Daily News points out that CoPoS extends CoWoS-R for Broadcom and CoWoS-L for NVIDIA and AMD.

Meanwhile, as Economic Daily News notes, TSMC unveiled a new CoWoS technology with a 9.5x reticle size at its North America Technology Symposium, with mass production scheduled for 2027. According to a report from Anue, this marks a significant upgrade from the current CoWoS-L’s 3.3x reticle size and the 8x version introduced last year, enabling the integration of 12 or more HBM stacks into a single package.

ASE

As Economic Daily News indicates, ASE already operates a mass production panel-level packaging line in Kaohsiung, utilizing 300x300mm panels and a fan-out process.

Powertech

The report also notes that Powertech has been active in this field the longest, achieving mass production as early as 2019. Its fan-out panel-level packaging technology, known as PiFO (Pillar Integration FO), is technically similar to TSMC’s CoPoS, as the report suggests.

Read more

• [News] TSMC Reportedly Gears Up for CoPoS Mass Production by 2029, Tapping NVIDIA as First Client
• [News] Wafer-Level Packaging Showdown: TSMC Scales up CoWoS Reticle Size, as Intel Readies Foveros-S

(Photo credit: TSMC)